Updates to the IPv6 Multicast Addressing Architecture
updates
Extracted elements (16)
Bits 17-20 of IPv6 multicast addresses, previously reserved, are redefined as generic flag bits (ff2) applicable to any multicast address. This allows addresses to be treated more uniformly and permits these bits to be assigned meanings in the future independent of multicast address type. The decision was triggered by the ADDR-FORMAT specification that proposed associating a meaning with one of the reserved bits.
The use of the last remaining flag bit in ff1 was considered but abandoned because it was not clear whether there are other usage scenarios for that flag. The document explicitly notes this as a rationale for leaving ff1's highest-order bit undefined rather than assigning it.
ff3x::/32 is not the only allowed SSM prefix range. When ff1 bits are set to 0011 the SSM range is ff3x::/32, but if additional ff1 flag bits are set (e.g., the most significant bit), other SSM prefix ranges such as ffbx::/32 are also valid.
Some implementations and specifications treat the 4 flag bits as a combined 4-bit integer rather than separate bits, leading to incorrect conclusions such as that ff3x::/32 is the only allowed SSM prefix block or that only ff70::/12 applies to Embedded-RP. This document's requirement to treat flag bits individually corrects these misinterpretations.
With the R-bit-based Embedded-RP definition, both ff70::/12 and fff0::/12 are valid Embedded-RP prefixes (whenever the R-bit is 1), superseding the RFC 3956 restriction that only ff70::/12 applies. The old guidance that implementations SHOULD NOT treat fff0::/12 as Embedded-RP is removed.
An Embedded-RP multicast address MUST have the R-bit set to 1 (replacing the old requirement that it be in the FF70::/12 prefix). It MUST also have the P-bit and T-bit both set to 1 when using the embedding defined in RFC 3956.
If the P flag is set to 1 in ff1 (indicating a unicast-prefix-based multicast address), then T MUST be set to 1; otherwise, the setting of T is defined in Section 2.7 of RFC 4291.
Implementations MUST treat flag bits as separate bits rather than interpreting their combined value as a 4-bit integer. This is required to unambiguously associate meanings with individual flags and avoid misinterpretation of allowed prefix ranges.
The ff2 'r' bits MUST each be sent as zero and MUST be ignored on receipt. This applies to all IPv6 multicast addresses using the updated format defined in this document.
To avoid loops and inconsistencies, for addresses with the R-bit set to 1, the Embedded-RP mapping MUST be considered the longest possible match and higher priority than any other mechanism. This replaces the old FF70::/12 range restriction.
When R=1 in ff1 (indicating an Embedded-RP multicast address), P MUST be set to 1 and consequently T MUST be set to 1, as this is a special case of unicast-prefix-based addresses per RFC 3306.
ff1 (flag field 1) is a 4-bit field at bits 13-16 of the IPv6 multicast address, renamed from 'flgs' in RFC 4291/3956. In the RFC 3306 context, ff1 carries bits X, Y, P, T; in the RFC 3956 context, ff1 carries X, R, P, T. X is for future assignment; Y is assigned meaning in RFC 3956.
ff2 (flag field 2) is a new 4-bit field at bits 17-20 of the IPv6 multicast address, defined by this document. All four bits ('rrrr') are reserved for future assignment as additional flag bits. These bits apply to all IPv6 multicast addresses.
The security considerations of RFC 3956, RFC 3306, and RFC 4291 apply unchanged. This document introduces no new security considerations beyond those already documented in those RFCs.
The updated RFC 3306 multicast address format is: 8 bits (0xFF prefix) | ff1 (4 bits) | scop (4 bits) | ff2 (4 bits) | rsvd (4 bits) | plen (8 bits) | network prefix (64 bits) | group ID (32 bits). The 'reserved' field from RFC 3306 is split into ff2 (4 bits) and rsvd (4 bits).
The updated RFC 3956 (Embedded-RP) multicast address format is: 8 bits (0xFF prefix) | ff1 (4 bits) | scop (4 bits) | ff2 (4 bits) | RIID (4 bits) | plen (8 bits) | network prefix (64 bits) | group ID (32 bits). ff1 carries X, R, P, T flags; ff2 carries four reserved r bits.